- instruction op-code fetch
- instruction op-code fetch Befehlslesezyklus m
English-German dictionary of Electrical Engineering and Electronics. 2013.
English-German dictionary of Electrical Engineering and Electronics. 2013.
Instruction pipeline — Pipelining redirects here. For HTTP pipelining, see HTTP pipelining. Basic five stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). In the fourth clock… … Wikipedia
Instruction cycle — An instruction cycle (sometimes called fetch and execute cycle, fetch decode execute cycle, or FDX) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what … Wikipedia
Instruction set — An instruction set, or instruction set architecture (ISA), is the part of the computer architecture related to programming, including the native data types, instructions, registers, addressing modes, memory architecture, interrupt and exception… … Wikipedia
Fetch-and-add — In computer science, the fetch and add CPU instruction is a special instruction that atomically modifies the contents of a memory location. It is used to implement Mutual exclusion and concurrent algorithms in multiprocessor systems.In… … Wikipedia
Instruction set simulator — An instruction set simulator (ISS) is a simulation model, usually coded in a high level programming language, which mimics the behavior of a mainframe or microprocessor by reading instructions and maintaining internal variables which represent… … Wikipedia
Threaded code — Not to be confused with multi threaded programming. In computer science, the term threaded code refers to a compiler implementation technique where the generated code has a form that essentially consists entirely of calls to subroutines. The code … Wikipedia
Burroughs large systems instruction set — The B5000 instruction set is the set of valid operations for the Burroughs large systems including the current (as of 2006) Unisys Clearpath/MCP systems. These unique machines have a distinctive design and instruction set. Each word of data is… … Wikipedia
Конвейер (процессоры)/Перевод — Пожалуйста, не удаляйте эту статью! В данный момент в ней идет работа по переводу основной английской версии для замены кошмарной русской. После завершения работы я объединю получившуюся статью с имеющейся русской версией. Простой пятиуровневый… … Википедия
Branch predictor — In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. This is called branch prediction. Branch predictors are… … Wikipedia
CDC 6600 — The CDC 6600 was a mainframe computer from Control Data Corporation, first delivered in 1964. It is generally considered to be the first successful supercomputer, outperforming its fastest predecessor, IBM 7030 Stretch, by about three times. It… … Wikipedia
PDP-10 — KL10 DA 1090 CPU and 6 Memory Modules The PDP 10 was a mainframe computer family[1] manufactured by Digital Equipment Corporation … Wikipedia